Programmable integrated circuits (ICs) are often used to implement digital logic operations according to user configurable input. Example programmable ICs include complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs often include several function blocks that are based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transmits signals between the function blocks. Many programmable ICs include hard-wired processors for performing certain functions. Alternatively, programmable ICs could also be programmed with soft processors in the programmable logic.
While the processors, either hard-wired or soft-programmed, are executing software, they may stop executing such software due to receiving an interrupt signal. When this occurs, the processor executes an interrupt handler in order to respond to the interrupt signal and to the event that generated the interrupt signal. Interrupts may be triggered to handle input/output information, processing events, and other events.
Performance metrics regarding interrupts are useful as an indicator of system health. For example, a metric that indicates how long an interrupt handler takes to begin executing may indicate whether the integrated circuit is “overloaded.” However, often, obtaining performance metrics regarding interrupts may be difficult or impossible. For example, because interrupt signals may be generated by an input/output device at a time that may not be synchronized with the system clock of the hard-wired processor, an accurate measure of the time from issuing an interrupt signal to beginning to execute an interrupt handler may be difficult to obtain.
As has been shown, what are needed in the art are improved techniques for obtaining performance metrics for interrupts.